Modeling, estimation and reduction of total leakage in scaled CMOS logic circuits

dc.contributor.author	Sachdeva, Nitin
dc.date.accessioned	2022-04-20T06:47:40Z
dc.date.available	2022-04-20T06:47:40Z
dc.date.issued	2021-10
dc.identifier.uri	http://localhost:8080/xmlui/handle/123456789/86
dc.description	Vashishath, Munish and Bansal, P K	en_US
dc.language.iso	en	en_US
dc.publisher	J C Bose University	en_US
dc.subject	Electronics Engineering	en_US
dc.title	Modeling, estimation and reduction of total leakage in scaled CMOS logic circuits	en_US
dc.type	Thesis	en_US