Modeling and simulation of low power VLSI interconnect

dc.contributor.author	Jadav, Sunil
dc.date.accessioned	2022-07-05T10:23:17Z
dc.date.available	2022-07-05T10:23:17Z
dc.date.issued	2018-04
dc.identifier.uri	http://localhost:8080/xmlui/handle/123456789/148
dc.description	Vashishath Munish, and Chandel Rajeevan	en_US
dc.language.iso	en	en_US
dc.publisher	JC Bose University	en_US
dc.subject	Electronics Engineering	en_US
dc.title	Modeling and simulation of low power VLSI interconnect	en_US
dc.type	Thesis	en_US